1. Technical Field
The present disclosure refers to a semiconductor device wherein a delay chain is integrated.
2. Description of the Related Art
A clock domain with a different phase with respect to the main clock of a device is often necessary to memory controller circuit applications. For example, the controller of DDR memories needs a strobe signal (DQS) with a delay of a ¼ of the period of the main clock to read/write the data to come from the memory or to send to the memory.
The problem of generating a clock with a desired phase with respect to the main clock can be solved by a delay chain. A usual circuit includes a multiplexer adapted to select a desired delay among the available delays. A controller can be used to select the corrected delay.
Such a circuit, however, has substantial implementation problems; in fact, it is very difficult to assure the monotonicity of the delays along all the chain in the presence of hundreds of delay elements. The routing can have a substantial impact on the shortest delay element and the monotonicity of the successive delays along all the chain can be broken.